1. Field of the Invention
This invention relates to the field of integrated circuits and, more particularly, to accommodating timing-based congestion within such devices.
2. Description of the Related Art
Very Large Scale Integrated (VLSI) circuits such as application specific integrated circuits (ASIC's) and field programmable gate arrays (FPGA's), have become increasingly complex and heterogeneous. Modern integrated circuits can include a variety of different components or resources including, but not limited to, block random access memories (RAM's), multipliers, processors, logic blocks, and the like. These components must be interconnected using a variety of different routing resources. The routing resources, however, are finite. As such, competition among components for wiring resources can dictate many aspects of an integrated circuit design such as area usage and timing performance.
Competition for wiring resources can be referred to as congestion. Modeling resource-based congestion has become an important aspect of integrated circuit design. A resource-based congestion model attempts to depict congestion within the integrated circuit design without regard for timing characteristics. Several resource-based congestion models have been proposed in the context of integrated circuit design. These models have included empirical models such as Rent's Rule, stochastic models that utilize probabilistic approaches, as well as the detection of congestion using a global router.
With respect to integrated circuit design, however, timing constraints and timing characteristics must be taken into account. In illustration, for an integrated circuit to function properly, particular connections and paths must conform to predetermined timing constraints. Additionally, some resources such as wires have more favorable timing characteristics than others. Such is the case as wires available within an integrated circuit can be of varying length and can be made of different materials. Thus, a signal propagating through one wire can require more or less time depending upon the length of the wire and the type of material from which the wire was made. There tends to be increased competition among components for wires having more favorable signal propagation characteristics, particularly in light of timing constraints.
Whenever demand for timing efficient resources exceeds the supply, timing-based congestion results. What is needed is a technique for dealing with timing-based congestion in the context of integrated circuit design.